1. Field of the Invention
The present invention is generally directed to the field of manufacturing semiconductor devices, and, more particularly, to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. However, the dimensions of modern semiconductor devices have, in some cases, been reduced below the wavelength of photolithography systems employed in the process of forming such features. In some cases, some features, such as, for example, gate electrode structures and active areas, are formed with corner regions. Due to the very small size of modern device features, and the limits of existing photolithography systems, devices may be formed with rounded corners, i.e., manufacturing-induced corner rounding.
FIGS. 1A-1B will be referenced to described the problems associated with manufacturing-induced corner rounding in connection with the formation of an illustrative gate electrode structure. FIG. 1A depicts an idealized gate electrode 10 comprised of a plurality of corner regions 12 and a gate contact 14. The gate electrode 10 has a critical dimension 16 in the area adjacent the corner regions 12 and a critical dimension 18 in portions of the gate electrode 10 remote from the corner regions 12. Ideally, the dimensions 16 and 18 are the same along the entire length of the gate electrode structure 10. FIG. 1B is an enlarged view of a gate electrode structure 10A that reflects some manufacturing-induced corner rounding 12A due to manufacturing processes. Depending upon the magnitude of the corner rounding, the dimension 16A of the gate electrode 10A may be significantly greater than the dimension 18A of the gate electrode structure 10A at distances remote from the corners 12A. Such dimensional variations can be problematic in modern, highly scaled transistor devices. For example, dimensional width variations of the gate electrode along its length may lead to the creation of non-uniform electric fields during the operation of a transistor, thereby impacting device performance.
FIGS. 2A-2B depict problems that manufacturing-induced corner rounding may cause in forming active regions in a substrate. Such active regions are typically formed by performing one or more ion implantation processes through a patterned layer of photoresist material. As shown in FIG. 2A, the active area 20 has a generally L-shaped configuration with a corner 22. FIG. 2B depicts an active area 20A exhibiting manufacturing-induced corner rounding 22A due to the manufacturing processes used to form the active area 20A. Such dimensional variations in the active area can also adversely affect device performance. For example, due to manufacturing-induced corner rounding, the area of the active area 20A may be less than or greater than the area anticipated by the design process, which, in turn, may adversely affect device performance.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.